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IEVref:714-03-07ID:
Language:enStatus: Standard
Term: digital switching delay
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Definition: difference in time between the arrival of a bit at a digital switching node and its subsequent departure

NOTE – Digital switching delay may be caused by buffering, synchronizing or time-slot interchange.


Publication date:1992-04
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Internal notes:2018-10-09: "time slot" replaced by "time-slot" in line with the TC 1 editorial decision taken in Frankfurt 1/2320e/RM. JGO
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